park jong hyun

park jong hyun

School of Electrical and Electronic Engineering, Yonsei University, South Korea

๐Ÿ“ Korea, Republic of
GPGPU Simulation - 2๋ถ€
GPGPU

GPGPU Simulation - 2๋ถ€

์ง€๋‚œ๋ฒˆ์— ์†Œ๊ฐœํ•œ GPGPU Simulation ์˜ ์‹ค์ œ ์˜ˆ๋ฅผ ๋ณด์—ฌ์ฃผ๊ฒ ๋‹ค. GPGPU-sim gpgpu-sim ํ™ˆํŽ˜์ด์ง€์— ๊ฐ€๋ณด๋ฉด, ๋ฉ”๋‰ด์–ผ์„ ๋ณด๊ณ  ์ฝ”๋“œ๋ฅผ ๋‹ค์šด ๋ฐ›์„ ์ˆ˜ ์žˆ๋‹ค. ๋ฆฌ๋ˆ…์Šค์—์„œ ์„ค์น˜ ๋ฐ ์‹คํ–‰์ด ๊ฐ€๋Šฅํ•˜๊ณ , CUDA๋Š” ์ตœ์‹  ๋ฒ„์ „์„ ์ง€์›ํ•˜์ง€ ์•Š๋Š”๋‹ค.... ๊ฐ„๋‹จํ•˜๊ฒŒ ๋Œ๋ฆฐ ์˜ˆ๋ฅผ ํ•œ๋ฒˆ ๋ณด์—ฌ๋“œ๋ฆผ. ์ปค๋„์ด ๋๋‚œ ํ›„์˜ ๊ฒฐ๊ณผ์ด๋‹ค. ์ปค๋„์ด ์ด ๋ช‡๊ฐœ์˜ instruction ์ธ์ง€ ๋ช‡ cycle์ด๋‚˜ ๊ฑธ๋ ธ๋Š”์ง€๋ฅผ ๋น„๋กฏํ•˜์—ฌ, ์–ด๋Š ๋ถ€๋ถ„์—์„œ stall

GPGPU Simulation - 1๋ถ€
GPGPU

GPGPU Simulation - 1๋ถ€

Simulation Simulation์„ ์ด์šฉํ•˜๋ฉด GPU์—†์ด CPU๋งŒ์œผ๋กœ๋„ CUDA (OpenCL) ์ฝ”๋“œ๋ฅผ ๋Œ๋ ค๋ณผ ์ˆ˜ ์žˆ๋‹ค. (๋ฌผ๋ก  emulation ๋งŒ์œผ๋กœ๋„ ๊ฐ€๋Šฅํ•˜๋‹ค.) CPU ์—์„œ GPU์˜ ๋™์ž‘์„ ์†Œํ”„ํŠธ์›จ์–ด๋กœ ๊ตฌํ˜„ simulator ๋“ค์ด ์žˆ๋‹ค. ๋Œ€ํ‘œ์ ์œผ๋กœ gpgpu-sim ๊ณผ multi2sim ์ด ์žˆ๋‹ค. Verilog๋กœ ๊ตฌํ˜„๋˜์–ด CPU๊ฐ€ ์•„๋‹Œ FPGA์—์„œ GPU๋ฅผ ์ง์ ‘ ๊ตฌ์›Œ๋ณผ์ˆ˜ ์žˆ๋Š” miaowgpu ๋„ ์žˆ๋‹ค. Simulation์˜ ์šฉ๋„ ์ด๋Ÿฌํ•œ simulation์€ ์‚ฌ์‹ค GPU๊ฐ€ ์—†๋Š” ์‚ฌ๋žŒ์„

GPGPU - 2๋ถ€
GPGPU

GPGPU - 2๋ถ€

GPGPU๋ž€?? - 2๋ถ€ GPGPU๋ฅผ ์œ„ํ•œ GPU ๊ตฌ์กฐ ์ง€๋‚œ 1๋ถ€์—์„œ ์–ธ๊ธ‰ํ•œ ๊ฒƒ ๊ณผ ๊ฐ™์ด GPU๋Š” ๊ทธ๋ž˜ํ”ฝ ์ฒ˜๋ฆฌ๋ฅผ ์œ„ํ•œ ํ•˜๋“œ์›จ์–ด์ด๊ณ  ๊ทธ๋ž˜ํ”ฝ ์ฒ˜๋ฆฌ๋Š” ๋Œ€๋Ÿ‰์˜ data-level-parallelism ์„ ๊ฐ€์ง„๋‹ค. ๋”ฐ๋ผ์„œ, ๊ธฐ๋ณธ์ ์œผ๋กœ SIMD ํ˜•ํƒœ์˜ ๊ตฌ์กฐ๋ฅผ ๊ฐ€์ง„๋‹ค. (SIMD = Single Instruction Multiple Data) ์œ„ ๊ทธ๋ฆผ ์ฒ˜๋Ÿผ ํ•˜๋‚˜์˜ instruction์„ ์—ฌ๋Ÿฌ๊ฐœ์˜ ALU๊ฐ€ ๋™์‹œ์— ์—ฌ๋Ÿฌ ๋ฐ์ดํ„ฐ๋ฅผ ์ฒ˜๋ฆฌ ํ•˜๋Š” ๊ฒƒ์„ SIMD ๋ผ๊ณ 

GPGPU - 1๋ถ€
GPGPU

GPGPU - 1๋ถ€

GPGPU (General Purpose computation on GPU) ๋ž€?? GPU ๋ถ€ํ„ฐ ์•Œ์•„๋ณด์ž (๊ฐ„๋‹จํ•˜๊ฒŒ) GPU (Graphics Processing Unit) ์€ ๋‹ค๋“ค ์•Œ๊ฒ ์ง€๋งŒ Graphics ์—ฐ์‚ฐ์„ ์œ„ํ•œ ์ „์šฉ ํ•˜๋“œ์›จ์–ด์ด๋‹ค. ๋ณดํ†ต ์™ธ์žฅ ๊ทธ๋ž˜ํ”ฝ์นด๋“œ์— ๋‹ฌ๋ฆฐ ๊ฐ€์šด๋ฐ ํฐ ์นฉ์ด๋‹ค. (๊ทธ๋ž˜ํ”ฝ์นด๋“œ๋Š” GPU๊ฐ€ ์•„๋‹ˆ๋ผ GPU์™€ ๋ฉ”๋ชจ๋ฆฌ๊ฐ€ ๊ฐ™์ด ๋‹ฌ๋ฆฐ ๋ณด๋“œ์ž„.) ์š”์ฆˆ์Œ์—๋Š” CPU์—๋„ ๋‚ด์žฅ GPU๊ฐ€ ๊ฐ™์ด ๋‹ฌ๋ ค๋‚˜์˜จ๋‹ค. Intel Core CPU ๊ณ„์—ด์—๋Š” HD graphics

Instruction-Level Parallelism (ILP)

Instruction-Level Parallelism (ILP) and Its Exploitation ILP: concepts and Challenges ILP -> hardware, software ๋‘๊ฐ€์ง€ ๋ฐฉ๋ฒ•์œผ๋กœ ๋Œ์–ด๋‚ธ๋‹ค. CPI < 1 branch ์™€ ๋‹ค์Œ branch ์‚ฌ์ด์˜ instruction ๋“ค์„ basic block ์ด๋ผ๊ณ  ํ•จ. ํ•œ basic block ์•ˆ์—์„œ ILP๋ฅผ ๋Œ์–ด๋‚ด๋Š” ๊ฒƒ์€ ํ•œ๊ณ„๊ฐ€ ์žˆ๊ธฐ ๋•Œ๋ฌธ์— ์—ฌ๋Ÿฌ๊ฐœ์˜ basic block ์—์„œ ILP๋ฅผ ์ด๋Œ์–ด๋‚ด์•ผํ•จ. ๊ฐ€์žฅ ๊ฐ„๋‹จํ•œ